Packages in combination with libraries are an excellent way that VHDL allows the digital designer to organize his or her code. By grouping functionality that belongs together, designs make much more sense and are leaner. They also allow you to write code that is reusable. You might find one particular package file being used again and again throughout your designs if it has some useful functions or constants.
It is preferable to put all of your component definitions in a single package file, rather than copy and pasting them everywhere the component is instantiated. This way, if the port map changes, only the package file and the actual instantiations need to be updated. Constants and types that appear repeatedly throughout your code should likely be grouped together in a package file. Or maybe be passed in your design using generics.
Functions and procedures need to exist both in the declaration section as well as the body section. Declare object of the file type 2. Declare variable of the type line 3. Open the file 4. Close the file. Comparing to basic way, here, it is not needed to define type of a file. Because that definition is already done in the package. If you look at the sources of the package, you will find it. There is defined a new type of a file: text. All data in files is treated as string.
Comparing to basic way, this part is new. Details are described here. For reading, first must be read a whole line from the file and then, values can be taken from that line one after another. For writing, first all values must be written to a line, and then, a whole line is written to a file. Now, access to values stored in the line variable is made by using read procedures. Every type has its own procedures. It is also possible to use a mixture of both approaches when calling a function, although this is not advisable.
The addition function which we used in our previous example is known as a pure function. This means the value it returns dependents only on its arguments. Prior to the VHDL standard, we also had to include the pure keyword in this type of function declaration.
However, this isn't required in all subsequent versions of VHDL. In contrast, impure functions return a value which isn't solely dependent on its arguments. As a result, we could call the function with the same arguments twice and get different return values. The only difference is the impure keyword at the beginning of the function declaration, as shown in the VHDL code snippet below.
However, one common use is when we require a function which generates random values to use in test benches. In order to do this, we typically use an algorithm which requires a se e d value. This initialises the underlying pseudo random algorithm , allowing it to create a sequence of apparently random numbers. The sequence of numbers changes if we give the algorithm a different seed. Therefore, we can set the value of the seed value using either a constant or a different function to generate different test patterns.
We can then use an impure function to generate the next number in the sequence for the given seed. The code snippet below shows the VHDL code for an impure function which generates a random number. The seed1 and seed2 values would be assigned externally to the function in this example. The uniform function is an inbuilt VHDL command which returns a random value between 0 and 1. Just like functions, we use procedures to implement small sections of code which we can reuse throughout our code.
Although functions and procedures perform similar function, there are some important differences between the two which effect when we use them. The first difference is that procedures don't return a value in the same way as a function.
However, we can use them to assign values to one or more output. The second major difference is that we can use wait statements and after statements within them. However, the process which calls the procedure can't have a sensitivity list if we wish to do this. These two features mean procedures are best used to implement simple tasks which are repeated several times in our code. When declaring a procedure in VHDL, we need to include a list of inputs, outputs and bidirectional parameters associated with the procedure.
We can include as many of each of these types as we need within the procedure. In addition, we can declare these as signals, variables or constant s. If this isn't explicitly defined, all inputs are treated as constants whilst all output and inout types are treated as variables. Let's consider a basic example to better demonstrate how to write a VHDL procedure. We will use a basic pulse generation function, which inverts a signal for a given amount of time.
To do this we require one input, which determines how long the pulse is, and an inout type to generate the pulse on. Whilst we only declare the data type in a function, we also declare the direction and the fact that we expect signals in this procedure. We can also see that a wait statement in used in this procedure. We use this to hold the pulse at the desired level. One final thing to say about this example is that we could use an output instead of the inout type. However, using the inout type means that we can create negative pulses.
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